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1.24c04芯片手册解读
2.纯verilog的i2c驱动
rst //高电平复位 clk //输入系统时钟 clk_div_cnt //i2c_scl分配系数:clk_div_cnt=clk/(5*i2c_scl)-1 scl_pad_i // SCL-line input scl_pad_o // SCL-line output (always 1'b0) scl_padoen_o // SCL-line output enable (active low) sda_pad_i // SDA-line input sda_pad_o // SDA-line output (always 1'b0) sda_padoen_o // SDA-line output enable (active low) i2c_addr_2byte // 地址位宽选择:1-->16bit ? 0-->8bit i2c_read_req // 发起读操作,高电平有效 i2c_read_req_ack // 读操作完成反馈高脉冲信号 i2c_write_req // 发写读操作,高电平有效 i2c_write_req_ack // 写操作完成反馈高脉冲信号 i2c_slave_dev_addr// I2c device address i2c_slave_reg_addr// I2c register address i2c_write_data // I2c write register data i2c_read_data // I2c read register data error // 读写错误反馈信号 3.24c04读写状态机设计
always @(posedge clk) begin if(~rstn) begin ST <='d0; i2c_read_req <='d0; i2c_write_req <='d0; i2c_slave_reg_addr<='d0; w_slave_reg_addr <='d0; r_slave_reg_addr <='d0; i2c_write_data <='d0; write_data_cnt <='d0; read_data_cnt <='d0; r_i2c_write_data <='d0; e2p_cnt <='d0; end else begin case(ST) 'd0: begin if(e2p_cnt==E2P_DELAY) begin //上电后延时250ms,让24c04准备好 ST<='d1; e2p_cnt<='d0; end else e2p_cnt<=e2p_cnt+'d1; end 'd1: begin if(i2c_write_req_ack) begin //写操作完成,进入等待写周期和地址、数据累加 i2c_write_req<='d0; ST<='d2; end else begin i2c_write_req<='d1; //发起写操作 i2c_write_data<=r_i2c_write_data; //给出写数据 i2c_slave_reg_addr<=w_slave_reg_addr; //给出写地址 end end 'd2: begin if(write_data_cnt=='d255) begin //写满255个数据后进入读数据状态 write_data_cnt <='d0; i2c_write_data <='d0; r_i2c_write_data <='d0; w_slave_reg_addr <='d0; i2c_slave_reg_addr<='d0; ST<='d4; end else begin if(wr_delay==WR_CYCEL) begin //延时4ms写周期，写数据和地址累加 write_data_cnt <=write_data_cnt+'d1; r_i2c_write_data<=r_i2c_write_data+'d1; w_slave_reg_addr<=w_slave_reg_addr+'d1; ST<='d3; end end end 'd3: ST<='d1; //打一排再循环写,保证写数据和地址在发起写操作前已经更新 'd4: begin if(i2c_read_req_ack) begin i2c_read_req<='d0; ST<='d5; end else begin i2c_read_req<='d1; //发起读操作 i2c_slave_reg_addr<=r_slave_reg_addr; //给出读地址 end end 'd5: begin if(read_data_cnt=='d255) begin //读完255个数据后重新开始状态机 read_data_cnt <='d0; r_slave_reg_addr<='d0; i2c_slave_reg_addr<='d0; ST<='d0; end else begin read_data_cnt <=read_data_cnt+'d1; r_slave_reg_addr <=r_slave_reg_addr+'d1; //读地址累加 ST<='d6; end end 'd6: ST<='d4; default: ST<='d0; endcase end end 4.上板调试验证
5.福利：工程源码获取
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