Chip发表：模拟集成电路的高效建模方法

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近日，西安电子科技大学杨银堂、谌东东团队以「A high-efficiency modeling method for analog integrated circuits」¹为题在Chip上发表研究论文，提出了一种基于卷积神经网络（CNN）的通用高效模拟IC建模方法。第一作者为谌东东和杨云淇，通讯作者为谌东东，李迪，杨银堂。

在先前研究中，训练数据（包括模拟集成电路的设计参数和性能指标）以向量形式罗列，这种方法未能全面考量空间布局与晶体管特性对模拟集成电路性能指标的影响2。本研究提出的稀疏拓扑映射方法通过将设计参数提取并映射至稀疏矩阵，将模拟集成电路性能指标作为该稀疏矩阵的标签。根据电路拓扑结构，选取横向晶体管最大数量作为矩阵长度，纵向晶体管最大数量作为矩阵宽度。晶体管尺寸被填入二维矩阵，剩余空间则以零填充，如图1所示。

本研究将特征提取划分为三个层级：晶体管级特征（TF）、电路模块级特征（MF）和集成电路级特征（ICF），如图1（b）所示。传统卷积神经网络(CNN)可通过局部卷积提取图像特征。本研究采用映射后的电路稀疏拓扑矩阵替代图像像素矩阵作为输入，提出的CNN-IC模型可实现”晶体管-电路模块-集成电路”特征的逐级提取。如图2所示。在该模型中，从局部晶体管到全局电路的关键特征被逐步提取，通过数学方程可精确描述模拟集成电路特征与性能指标间的非线性映射关系。

图1 | 整体方法框架图。（a）模拟集成电路稀疏拓扑映射示意图。（b）模拟集成电路特征提取示意图。（c）两级运算放大器电路稀疏拓扑映射矩阵。（d）带隙基准电路稀疏拓扑映射矩阵。

图2 | CNN-IC结构示意图。（a）CNN-IC模型的整体结构。（b）卷积层示意图。（c）池化层示意图。（d）全连接层示意图。

采用二级运放和带隙基准电路对所提出的建模方法进行验证。结果表明，经过训练的CNN-IC模型对二级运放电路性能指标的拟合精度超过99.9%，对带隙基准电路的拟合精度超过了99%。本团队还建立了人工神经网络（ANN）、支持向量机（SVM）、卷积神经网络（CNN）、残差神经网络（ResNet）、深度神经网络（DNN）和Transformer模型3–5，与CNN-IC模型进行对比，如图3和4所示。从图中可以看出，本文提出的CNN-IC模型具有最佳准确率表现。与其他机器学习模型相比，CNN-IC模型的损失值下降迅速且能稳定达到最小值，这表明该模型具有优异的训练效率和泛化能力。这一优势源于构建数据集时，STM矩阵同时考虑了模拟集成电路的空间特性和晶体管特性，使得CNN-IC模型能利用更多信息进行训练，从而有效建立设计参数与性能指标之间的关联。

图3 | 所提出的CNN-IC模型在二级运放电路中的验证结果。（a-d）不同机器学习模型拟合精度的比较。（e-h）CNN-IC模型相对误差的正态统计结果。（i-j）不同机器学习模型经过2000次迭代后的损失值比较。

图4 | 所提出的CNN-IC模型在带隙基准电路中的验证结果。（a-d）不同机器学习模型拟合精度的比较。（e-h）CNN-IC模型相对误差的正态统计结果。（i-j）不同机器学习模型经过2000次迭代后的损失值比较。

A high-efficiency modeling method for analog integrated circuits¹

In the previous research, the training data, including the design parameters and performance metrics of analog integrated circuits (ICs), were listed in a vector form, which does not comprehensively consider the effect of the spatial and transistor characteristics on performance metrics of analog ICs2. In this research, the sparse topology mapping method (STM) was proposed to extract and map the design parameters into a sparse matrix, and the performance metrics of analog ICs were the labels for the sparse matrix. According to the circuit topology structure, the maximum number of transistors in the lateral direction was selected as the length of the matrix, and the maximum number of transistors in the vertical direction selected as the width of the matrix. The sizes of transistors were filled into the two-dimensional matrix, while the remaining space was filled with zero, as shown in Fig. 1.

Fig. 1 | Features analyzation of analog ICs. (a) Diagram of the STM for analog ICs. (b) Diagram of the feature extraction for analog ICs in the CNN. (c) STM matrix for the TSMCOA circuit. (d) STM matrix for the BGR circuit.

In this research, the features’ extraction can be divided into three levels, including transistor-level feature (TF), circuit module-level feature (MF), and integrated circuit-level feature (ICF), as shown in Fig. 1(b). For traditional convolutional neural network (CNN), image features can be extracted through local convolution. In this paper, the established mapped circuit sparse topology matrix was used to replace the image pixel matrix as input. Based on the feature analyzation of analog ICs, the CNN model with three convolutional kernels was constructed to extract the “transistor-circuit module-integrate circuit” features level by level, which is shown in Fig. 2. In the constructed CNN-IC model, the critical circuit features from local transistors to global circuits were gradually extracted, and the nonlinear mapping relationship between features and performance metrics of analog ICs can be accurately described by mathematical equations.

Fig. 2 | Structure of the proposed CNN. (a) Total structure of the proposed CNN-IC model. (b) Diagram of the convolutional layer. (c) Diagram of the max pooling layer. (d) Diagram of the fully connected layer.

The proposed modeling method was validated by the two-stage Miller compensation operational amplifier (TSMCOA) and the bandgap reference (BGR) circuit. The accuracy of the trained CNN-IC models for the performance metrics of the TSMCOA and BGR circuits is above 99.9%, and 99%, respectively. To further verify the effectiveness of the proposed CNN-IC models, the artificial neural network (ANN), support vector machine (SVM), CNN, residual neural network (ResNet), deep neural network (DNN), and Transformer models were established and compared with the CNN-IC model, as shown in Fig. 3 and 43–5. Obviously, the accuracy of the proposed CNN-IC model is the best. Compared with other machine learning models, the loss value of the CNN-IC model rapidly decreases and stably achieves the minimum, which implies that the CNN-IC model has the excellent training efficiency and generalization ability. This is attributed to the fact that both the spatial and transistor characteristics of analog ICs are considered in the STM matrix during the construction of dataset and more information can be used to train the CNN-IC model, which is beneficial to establish the connection between design parameters and performance metrics of analog ICs.

Fig. 3 | Results of the proposed CNN-IC model for TSMCOA circuit. (a-d) Comparisons of fitting accuracy for different machine learning models. (e-h) Normal statistics results of the relative errors for the CNN-IC model. (i-j) Comparisons of loss values for different machine learning models with 2000 iterations.

Fig. 4 | Results of the proposed CNN-IC model for BGR circuit. (a-c) Comparisons of fitting accuracy for different machine learning models. (d-f) Normal statistics results of the relative errors for the CNN-IC model. (g-i) Comparisons of loss values for different machine learning models with 2000 iterations.

参考文献

1. Chen, D. et al. A high-efficiency modeling method for analog integrated circuits. Chip 4, (2025).

2. Yang, Y. et al. The high-efficiency optimization design method for two-stage miller compensated operational amplifier. IEEE Trans. Circuits Syst. II: Express Br. 71(4), 2029-2033 (2024).

3. Rashid, R. & Nambath, N. Area optimization of two stage miller compensate opamp in 65 nm using Hybrid PSO. IEEE Trans. Circuits Syst. II: Express Br. 69,199-203 (2022).

4. Li, Y. et al. An artificial neural network assisted optimization system for analog design space exploration. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 39(10), 2640-2653 (2020).

5. Yang Y., Chen D., Wang X., et al., A high-efficiency codesign method for bandgap circuit by submodule optimization. Int. J. Circuit Theory Appl. 24, (2025).

论文链接：

https://www.sciencedirect.com/science/article/pii/S00097

扫码阅读原文

作者简介

谌东东，1989年出生于中国山东省潍坊市。他于2018年获得中南大学机械工程博士学位。他是西安电子科技大学微电子学院的副教授。他目前的研究兴趣包括惯性传感器、压电器件、集成电路、3D集成微系统及其应用的数学建模和智能设计。

Dongdong Chen was born in Weifang, Shandong Province, China, in 1989. He received the Ph. D degree in mechanical engineering from Central South University in 2018. He is an associate professor within the School of Microelectronics at Xidian University. His current research interests include the mathematical modelling and intelligent design of inertial sensors, piezoelectric devices, integrated circuits, 3D integrated microsystem and their applications.

杨云淇，2000年出生于河北邯郸。他在西安工业大学自动化专业2022年学士学位。目前在西安电子科技大学集成电路学部攻读博士学位。他的研究方向是模拟电路设计和智能化方法。

Yunqi Yang was born in Handan, Hebei, China, in 2000. He received the B.E. degree in automation from Xi’an technology university in 2022. He is currently pursuing the doctor’s degree in electronic information engineering with Xidian University, Xi’an, China. His research direction is analog circuit design and intelligence.

王祥龙，1997年出生于中国四川省绵阳市。2020年，他获得了成都信息技术大学微电子科学与工程学士学位。他目前正在西安电子科技大学攻读集成电路科学与工程博士学位。他的研究方向是高精度超宽带定位系统和三维集成电路/系统设计。

Xianglong Wang was born in Mianyang, Sichuan Province, China, in 1997. He received the B.S. degree in microelectronics science and engineering from Chengdu University of Information Technology, Chengdu, China, in 2020. He is currently pursuing the Ph.D. degree in Integrated circuit science and engineering from Xidian University. His research directions are high-accuracy UWB positioning system and 3-dimensional integrated circuit/system design.